

`define Inst_RAM_22x128_SP_RF_DATA_WIDTH	22
`define Inst_RAM_22x128_SP_RF_ADDR_WIDTH 	7
`timescale 1ns/1ps

module Inst_RAM_22x128_SP_RF(
	ena,
	clka, 
	addra, 
	dina, 
	douta, 
	wea
);


input clka;
input ena;
input [`Inst_RAM_22x128_SP_RF_ADDR_WIDTH-1:0]addra; 
input [`Inst_RAM_22x128_SP_RF_DATA_WIDTH-1:0]dina; 
output [`Inst_RAM_22x128_SP_RF_DATA_WIDTH-1:0]douta; 
input wea;


// module rf_sp_22_128 (Q, CLK, CEN, WEN, A, D, EMA, EMAW, RET1N);	// 9


  wire [`Inst_RAM_22x128_SP_RF_DATA_WIDTH-1:0] Q;
  wire  CLK;
  wire  CEN;
  wire  WEN;
  wire [`Inst_RAM_22x128_SP_RF_ADDR_WIDTH-1:0] A;
  wire [`Inst_RAM_22x128_SP_RF_DATA_WIDTH-1:0] D;
  wire [2:0] EMA;
  wire [1:0] EMAW;
  wire  RET1N;


assign CLK = clka;
assign #1 CEN  = ~ena;
assign #1 WEN  = ~wea;
assign #1 A    = addra;
assign #1 D    = dina;
assign douta = Q;			// 6


assign EMA = 3'b010;
assign EMAW = 2'b00;
assign RET1N = 1'b1;		// 3


// module rf_sp_22_128 (Q, CLK, CEN, WEN, A, D, EMA, EMAW, RET1N);

rf_sp_22_128 rf_sp_22_128_u0 (.Q(Q), .CLK(CLK), .CEN(CEN), .WEN(WEN), .A(A), .D(D), .EMA(EMA), .EMAW(EMAW), .RET1N(RET1N));

endmodule

	




